1. Field of the Invention
The invention relates in general to an application of a partial reverse mask. More particularly, the present invention relates to a method of applying the partial reverse mask on a dielectric layer with a low dielectric constant.
2. Description of the Related Art
In the manufacturing of very large scale integrated (VLSI) semiconductors, multilevel interconnects, fabricated from two or more metal interconnect layers above a wafer, are quite common. The purpose of having multilevel interconnects is to increase three-dimensional wiring line structures so that the densely packed devices can be properly linked together. In general, the first layer of wiring lines can be made from polysilicon or a metal, and can be used to electrically couple the source/drain regions of devices in the substrate. In other words, through the formation of vias, devices in substrate are electrically connected together. For connecting more devices, a second or more layers of metallic wiring can be used. With the increase in level of integration, a capacitor effect between metallic lines, which can lead to RC delay and cross talk between vias, increases correspondingly. Consequently, speed of conduction between metallic lines is slower. Therefore, to reduce the capacitor effect, a type of low-k dielectric material is now commonly used for forming inter-layer dielectric or inter-metal dielectric (ILD/IMD) layers. The low-k dielectric material, for example, FSG, is quite effective in reducing RC delay between metallic lines. In practice, however, there are a number of technical problems regarding the use of low-k dielectric that still need to be addressed. One of them is the poor adhesive ability of the low-k material.